View ADRF6702_1711614.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1550 mhz to 2650 mhz quadrature modulator with 2100 mhz to 2600 mhz frac-n pll and integrated vco adrf6703 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features iq modulator with integrated fractional-n pll rf output frequency range: 1550 mhz to 2650 mhz internal lo frequency range: 2100 mhz to 2600 mhz output p1db: 14.2 dbm @ 2140 mhz output ip3: 33.2 dbm @ 2140 mhz noise floor: ?159.6 dbm/hz @ 2140 mhz baseband bandwidth: 750 mhz (3 db) spi serial interface for pll programming integrated ldos and lo buffer power supply: 5 v/240 ma 40-lead 6 mm 6 mm lfcsp applications cellular communications systems gsm/edge, cdma2000, w-cdma, td-scdma, lte broadband wireless access systems satellite modems general description the adrf6703 provides a quadrature modulator and synthesizer solution within a small 6 mm 6 mm footprint while requiring minimal external components. the adrf6703 is designed for rf outputs from 1550 mhz to 2650 mhz. the low phase noise vco and high performance quadrature modulator make the adrf6703 suitable for next generation communication systems requiring high signal dynamic range and linearity. the integration of the iq modulator, pll, and vco provides for significant board savings and reduces the bom and design complexity. the integrated fractional-n pll/synthesizer generates a 2 f lo input to the iq modulator. the phase detector together with an external loop filter is used to control the vco output. the vco output is applied to a quadrature divider. to reduce spurious components, a sigma-delta (-) modulator controls the programmable pll divider. the iq modulator has wideband differential i and q inputs, which support baseband as well as complex if architectures. the single-ended modulator output is designed to drive a 50 load impedance and can be disabled. the adrf6703 is fabricated using an advanced silicon- germanium bicmos process. it is available in a 40-lead, exposed-paddle, pb-free, 6 mm 6 mm lfcsp package. performance is specified from ?40c to +85c. a lead-free evaluation board is available. table 1. part no. internal lo range 3 db rf out balun range ADRF6702 1550 mhz 1200 mhz 2150 mhz 2400 mhz adrf6703 2100 mhz 1550 mhz 2600 mhz 2650 mhz functional block diagram mux rset cp vtune losel lon lop qn 2:1 mux vco core qp temp sensor decl3 decl2 decl1 enop buffer buffer rfout nc notes 1. nc = no connect. do not connect to this pin. v cc1 v cc2 v cc3 v cc4 v cc5 v cc6 ? + charge pump 250a, 500a (default), 750a, 1000a prescaler 2 le clk spi interface data muxout 2 0/90 refin gnd adrf6703 29 v cc7 34 26 16 39 3 5 4 8 6 14 13 12 38 37 36 7 11 15 20 21 23 24 25 28 30 31 35 2 9 40 ip in 27 17 10 1 22 phase frequency detector third-order fractional interpolator fraction reg modulus integer reg n counter 21 to 123 2 2 4 divider 2 18 19 32 33 08570-001 figure 1.
adrf6703 rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing characteristics ................................................................ 6 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 16 pll + vco.................................................................................. 16 basic connections for operation............................................. 16 external lo ................................................................................. 16 loop filter ................................................................................... 17 dac-to-iq modulator interfacing .......................................... 18 adding a swing-limiting resistor ........................................... 18 iq filtering .................................................................................. 19 baseband bandwidth ................................................................. 19 device programming and register sequencing..................... 19 register summary .......................................................................... 20 register description....................................................................... 21 register 0integer divide control (default: 0x0001c0) .... 21 register 1modulus divide control (default: 0x003001).. 22 register 2fractional divide control (default: 0x001802).....22 register 3- modulator dither control (default: 0x10000b).................................................................................... 23 register 4pll charge pump, pfd, and reference path control (default: 0x0aa7e4)................................................... 24 register 5lo path and modulator control (default: 0x0000d5) ................................................................................... 26 register 6vco control and vco enable (default: 0x1e2106).................................................................................... 27 register 7external vco enable ........................................... 27 characterization setups................................................................. 28 evaluation board ............................................................................ 30 evaluation board control software......................................... 30 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 6/11revision 0: initial version
adrf6703 rev. 0 | page 3 of 36 specifications v s = 5 v; t a = 25c; baseband i/q amplitude = 1 v p-p differential sine waves in quadrature with a 500 mv dc bias; baseband i/q frequency (f bb ) = 1 mhz; f pfd = 38.4 mhz; f ref = 153.6 mhz at +4 dbm re:50 (1 v p-p); 130 khz loop filter, unless otherwise noted. table 2. parameter test conditions/comments min typ max unit operating frequency range iq modulator (3 db rf output range) 1550 2650 mhz pll lo range 2100 2600 mhz rf output = 2140 mhz rfout pin nominal output power baseband viq = 1 v p-p differential 4.95 dbm iq modulator voltage gain rf output divi ded by baseband input voltage 0.95 db op1db 14.2 dbm carrier feedthrough ?44.1 dbm sideband suppression ?52.3 dbc quadrature error +0.0/?0.6 degrees i/q amplitude balance 0.04 db second harmonic p out ? p (f lo (2 f bb )) ?63.0 dbc third harmonic p out ? p (f lo (3 f bb )) ?52.0 dbc output ip2 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out ?2 dbm per tone 70.1 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out ?2 dbm per tone 33.2 dbm noise floor i/q inputs = 0 v differential with 500 mv dc bias, 20 mhz carrier offset ?159.6 dbm/hz rf output = 2300 mhz rfout pin nominal output power baseband viq = 1 v p-p differential 4.48 dbm iq modulator voltage gain rf output divi ded by baseband input voltage 0.48 db op1db 13.5 dbm carrier feedthrough ?46.0 dbm sideband suppression ?44.0 dbc quadrature error ?0.25/?0.98 degrees i/q amplitude balance 0.06 db second harmonic p out ? p (f lo (2 f bb )) ?67.0 dbc third harmonic p out ? p (f lo (3 f bb )) ?53.0 dbc output ip2 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out ?2 dbm per tone 68.6 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out ?2 dbm per tone 32.7 dbm noise floor i/q inputs = 0 v differential with 500 mv dc bias, 20 mhz carrier offset ?159.7 dbm/hz rf output = 2600 mhz rfout pin nominal output power baseband viq = 1 v p-p differential 2.75 dbm iq modulator voltage gain rf output divide d by baseband input voltage ?1.25 db op1db 11.8 dbm carrier feedthrough ?46.8 dbm sideband suppression ?35.3 dbc quadrature error 0.56/2.3 degrees i/q amplitude balance 0.06 db second harmonic p out ? p (f lo (2 f bb )) ?63.0 dbc third harmonic p out ? p (f lo (3 f bb )) ?51.0 dbc output ip2 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out ?2 dbm per tone 62.0 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out ?2 dbm per tone) 29.2 dbm noise floor i/q inputs = 0 v differential with 500 mv dc bias, 20 mhz carrier offset ?161.7 dbm/hz synthesizer specifications synthe sizer specifications referenced to the modulator output internal lo range 2100 2600 mhz figure of merit (fom) 1 ?222.0 dbc/hz/hz
adrf6703 rev. 0 | page 4 of 36 parameter test conditions/comments min typ max unit reference characteristics re fin, muxout pins refin input frequency 12 160 mhz refin input capacitance 4 pf phase detector frequency 20 40 mhz muxout output level low (lock detect output selected) 0.25 v high (lock detect output selected) 2.7 v muxout duty cycle 50 % charge pump charge pump current programmable to 250 a, 500 a, 750 a, 1000 a 500 a output compliance range 1 2.8 v phase noise (frequency = 2140 mhz, f pfd = 38.4 mhz) closed loop operation (see figure 35 for loop filter design) 10 khz offset ?105.3 dbc/hz 100 khz offset ?103.1 dbc/hz 1 mhz offset ?127.9 dbc/hz 10 mhz offset ?149.7 dbc/hz integrated phase noise 1 khz to 10 mhz integration bandwidth 0.29 rms reference spurs f pfd /2 ?110 dbc f pfd ?102.0 dbc f pfd 2 ?87.2 dbc f pfd 3 ?90.4 dbc f pfd 4 ?98.4 dbc phase noise ( frequency = 2300 mhz, f pfd = 38.4 mhz) closed loop operation (see figure 35 for loop filter design) 10 khz offset ?103.5 dbc/hz 100 khz offset ?102.2 dbc/hz 1 mhz offset ?128.4 dbc/hz 10 mhz offset ?149.5 dbc/hz integrated phase noise 1 khz to 10 mhz integration bandwidth 0.295 rms reference spurs f pfd /2 ?110.7 dbc f pfd ?102.3 dbc f pfd 2 ?85.5 dbc f pfd 3 ?92.4 dbc f pfd 4 ?101.1 dbc phase noise ( frequency = 2600 mhz, f pfd = 38.4 mhz) closed loop operation (see figure 35 for loop filter design) 10 khz offset ?98.8 dbc/hz 100 khz offset ?100.2 dbc/hz 1 mhz offset ?129.2 dbc/hz 10 mhz offset ?151.0 dbc/hz integrated phase noise 1 khz to 10 mhz integration bandwidth 0.37 rms reference spurs f pfd /2 ?110.6 dbc f pfd ?106.5 dbc f pfd 2 ?88.6 dbc f pfd 3 ?92.4 dbc f pfd 4 ?102.5 dbc rf output harmonics measured at rfout, frequency = 2140 mhz second harmonic ?41 dbc third harmonic ?65 dbc lo input/output lop, lon output frequency range divide by 2 circuit in lo path enabled 2100 2600 mhz divide by 2 circuit in lo path disabled 4200 5200 mhz lo output level at 2140 mhz 2 lo or 1 lo mode , into a 50 load, lo buffer enabled 0.1 dbm lo input level externally applie d 2 lo, pll disabled 0 dbm lo input impedance externally appl ied 2 lo, pll disabled 50
adrf6703 rev. 0 | page 5 of 36 parameter test conditions/comments min typ max unit baseband inputs ip, in, qp, qn pins i and q input dc bias level 400 500 600 mv bandwidth p out ?7 dbm, rf flatness of iq modulator output calibrated out 0.5 db 350 mhz 3 db 750 mhz differential input impedance frequency = 1 mhz 2 945 differential input capacitance frequency = 1 mhz 2 1 pf logic inputs clk, data, le, enop, losel input high voltage, v inh 1.4 3.3 v input low voltage, v inl 0 0.7 v input current, i inh /i inl 0.1 a input capacitance, c in 5 pf temperature sensor vptat voltage measured at muxout output voltage t a = 25 c, rl 10 k (lo buffer disabled) 1.624 v temperature coefficient t a = ?40 c to +85 c, rl 10 k 3.65 mv/ c power supplies vcc1, vcc2, vcc3, vcc4, vcc5, vcc6, vcc7 voltage range 4.75 5 5.25 v supply current normal tx mode (pll and iqmo d enabled, lo buffer disabled) 240 ma tx mode using external lo input (internal vco/pll disabled) 134 ma tx mode with lo buffer enabled 290 ma power-down mode 22 a 1 the figure of merit (fom) is computed as phase noise (dbc/hz) C 10log10(f pfd ) C 20log10(f lo /f pfd ). the fom was measured across the full lo range, with f ref = 80 mhz, f ref power = 10 dbm (500 v/s sl ew rate) with a 40 mhz f pfd . the fom was computed at 50 khz offset. 2 refer to figure 40 for plot of input impedance over frequency.
adrf6703 rev. 0 | page 6 of 36 timing characteristics table 3. parameter limit unit test conditions/comments t 1 20 ns min le to clk setup time t 2 10 ns min data to clk setup time t 3 10 ns min data to clk hold time t 4 25 ns min clk high duration t 5 25 ns min clk low duration t 6 10 ns min clk to le setup time t 7 20 ns min le pulse width clk data le db23 (msb) db22 db2 db1 (control bit c2) (control bit c3) db0 (lsb) (control bit c1) t 2 t 3 t 7 t 6 t 1 t 4 t 5 08570-002 figure 2. timing diagram
adrf6703 rev. 0 | page 7 of 36 absolute maximum ratings table 4. parameter rating supply voltage (vcc1 to vcc7) 5.5 v digital i/o, clk, data, le ?0.3 v to +3.6 v lop, lon 18 dbm ip, in, qp, qn ?0.5 v to +1.5 v refin ?0.3 v to +3.6 v ja (exposed paddle soldered down) 1 35c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 per jdec standard jesd 51-2.
adrf6703 rev. 0 | page 8 of 36 pin configuration and fu nction descriptions pin 1 indicator notes 1. nc = no connect. do not connect to this pin. 2 . the exposed paddle should be soldered to a low impedance ground plane. 1 vcc1 2 decl1 3 cp 4 gnd 5 rset 6 refin 7 gnd 8 muxout 9 decl2 10 vcc2 23 gnd 24 nc 25 gnd 26 rfout 27 vcc5 28 gnd 29 vcc6 30 gnd 22 vcc4 21 gnd 1 1 g n d 1 2 d a t a 1 3 c l k 1 5 g n d 1 7 v c c 3 1 6 e n o p 1 8 q p 1 9 q n 2 0 g n d 1 4 l e 3 3 i p 3 4 v c c 7 3 5 g n d 3 6 l o s e l 3 7 l o n 3 8 l o p 3 9 v t u n e 4 0 d e c l 3 3 2 i n 3 1 g n d top view (not to scale) adrf6703 08570-003 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1, 10, 17, 22, 27, 29, 34 vcc1, vcc2, vcc3, vcc4, vcc5, vcc6, vcc7 power supply pins. the power supply voltage range is 4.75 v to 5.25 v. drive all of these pins from the same power supply voltage. decouple each pin with 100 pf and 0.1 f capacitors located close to the pin. 2 decl1 decoupling node for internal 3.3 v ldo. decouple this pin with 100 pf and 0.1 f capacitors located close to the pin. 3 cp charge pump output pin. connect vtune to this pin through the loop filter. if an external vco is being used, connect the output of the loop filter to the vcos voltage control pin. the pll control loop should then be closed by routing the vcos frequency output back into the adrf6703 through the lon and lop pins. 4, 7, 11, 15, 20, 21, 23, 25, 28, 30, 31, 35 gnd ground. connect these pins to a low impedance ground plane. 24 nc do not connect to this pin. 5 rset charge pump current. the nominal charge pump current can be set to 250 a, 500 a, 750 a, or 1000 a using db10 and db11 of re gister 4 and by setting db18 to 0 (cp reference source). in this mode, no external rset is required. if db18 is set to 1, the four nominal charge pump currents (i nominal ) can be externally tweaked according to the following equation: ? ? ? ? ? ? ? ? ? = 8.37 4.217 nominal cp set i i r where i cp is the base charge pump current in microamps. for further details on the charge pump current, see the register 4pll charge pump, pfd, and reference path control section. 6 refin reference input. the nominal input level is 1 v p-p. input range is 12 mhz to 160 mhz. this pin has high input impedance and should be ac-coupled. if refin is being driven by laboratory test equipment, the pin should be externally terminated with a 50 resistor (place the ac-coupling capacitor between the pin and the resistor). when driven from an 50 rf signal generator, the recommended input level is 4 dbm. 8 muxout multiplexer output. this output allows a digital lock detect signal, a voltage proportional to absolute temperature (vpt at), or a buffered, frequency-scaled reference signal to be accessed externally. the output is selected by programming db21 to db23 in register 4. 9 decl2 decoupling node for 2.5 v ldo. connect 100 pf, 0.1 f, and 10 f capacitors between this pin and ground. 12 data serial data input. the serial data input is loaded msb fi rst with the three lsbs being the control bits.
adrf6703 rev. 0 | page 9 of 36 pin no. mnemonic description 13 clk serial clock input. this serial clock input is used to clock in th e serial data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. maximum clock frequency is 20 mhz. 14 le latch enable. when the le input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word. 16 enop modulator output enable/disable. see table 6 . 18, 19, 32, 33 qp, qn, in, ip modulator baseband inputs. differential in -phase and quadrature baseband inputs. these inputs should be dc-biased to 0.5 v. 26 rfout rf output. single-ended, 50 internally bias ed rf output. rfout must be ac-coupled to its load. 36 losel lo select. this digital input pin determines whether the lop and lon pins operate as inputs or outputs. this pin sh ould not be left floating. lo p and lon become inputs if the losel pin is set low and the ldrv bit of register 5 is set low. external lo drive must be a 2 lo. in addition to setting lo sel and ldrv low and providing an external 2 lo, the lxl bit of register 5 (db4) must be set to 1 to direct th e external lo to the iq modulator. lon and lop beco me outputs when losel is hi gh or if the ldrv bit of register 5 (db3) is set to 1. a 1 lo or 2 lo output can be selected by setting the ldiv bit of register 5 (db5) to 1 or 0 respectively (see table 7 ). 37, 38 lon, lop local oscillator input/output. the internally generated 1 lo or 2 lo is available on these pins. when internal lo generation is disabled, an extern al 1 lo or 2 lo can be applied to these pins. 39 vtune vco control voltage input. this pin is driv en by the output of the loop filter. nominal input voltage range on this pin is 1.3 v to 2.5 v. if the external vco mode is activated, this pin can be left open. 40 decl3 decoupling node for vco ldo. connect a 100 pf capacitor and a 10 f capacitor between this pin and ground. ep exposed paddle. the exposed paddle should be soldered to a low impedance ground plane. table 6. enabling rfout enop register 5 bit db6 rfout x 1 0 disabled 0 x 1 disabled 1 1 enabled 1 x = dont care. table 7. lo port configuration 1 , 2 lon/lop function losel register 5 bit db5(ldiv) register 5 bit db4(lxl) register 5 bit db3 (ldrv) input (2 lo) 0 x 1 0 output (disabled) 0 x 0 0 output (1 lo) 0 0 0 1 output (1 lo) 1 0 0 0 output (1 lo) 1 0 0 1 output (2 lo) 0 1 0 1 output (2 lo) 1 1 0 0 output (2 lo) 1 1 0 1 1 x = dont care. 2 losel should not be left floating.
adrf6703 rev. 0 | page 10 of 36 typical performance characteristics v s = 5 v; t a = 25c; baseband i/q amplitude = 1 v p-p differential sine waves in quadrature with a 500 mv dc bias; baseband i/q frequency (f bb ) = 1 mhz; f pfd = 38.4 mhz; f ref = 153.6 mhz at +4 dbm re:50 (1 v p-p); 130 khz loop filter, unless otherwise noted. 0 1 2 3 4 5 6 7 8 9 10 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 ssb output power (dbm) lo frequency (mhz) t a = ?40c t a = +25c t a = +85c 08570-104 figure 4. single sideband (ssb) output power (p out ) vs. lo frequency (f lo ) and temperature; multiple devices shown 10 11 12 13 14 15 16 17 18 19 20 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 1db output compression (dbm) lo frequency (mhz) v s = 5.25v v s = 4.75v v s = 5.00v 08570-105 figure 5. ssb output 1db compression point (op1db) vs. lo frequency (f lo ) and temperature; multiple devices shown ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.1 1 10 ssb output power (dbm) second-order distortion (dbc), third-order distortion (dbc), carrier feedthrough (dbm), sideband suppression (dbc) baseband input voltage (v p-p differential) carrier feedthrough (dbm) third-order distortion (dbc) ssb output power (dbm) sideband suppression (dbc) second-order distortion (dbc) 08570-106 figure 6. ssb output power, second- and third-order distortion, carrier feedthrough and sideband suppression vs. baseband differential input voltage (f out = 2140 mhz) 0 1 2 3 4 5 6 7 8 9 10 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 ssb output power (dbm) lo frequency (mhz) v s = 5.25v v s = 4.75v v s = 5.00v 08570-107 figure 7. single sideband (ssb) output power (p out ) vs. lo frequency (f lo ) and power supply; multiple devices shown 10 11 12 13 14 15 16 17 18 19 20 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 1db output compression (dbm) lo frequency (mhz) v s = 5.25v v s = 4.75v v s = 5.00v 08570-108 figure 8. ssb output 1db compression point (op1db) vs. lo frequency (f lo ) and power supply 15 10 5 0 ?5 ?10 ?15 ?20 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.1 1 10 ssb output power (dbm) second-order distortion (dbc), third-order distortion (dbc), carrier feedthrough (dbm), sideband suppression (dbc) baseband input voltage (v p-p differential) carrier feedthrough (dbm) third-order distortion (dbc) ssb output power (dbm) sideband suppression (dbc) second-order distortion (dbc) 08570-109 figure 9. ssb output power, second- and third-order distortion, carrier feedthrough and sideband suppression vs. baseband differential input voltage (f out = 2600 mhz)
adrf6703 rev. 0 | page 11 of 36 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 carrier feedthrough (dbm) lo frequency (mhz) t a = ?40c t a = +25c t a = +85c 08570-110 figure 10. carrier feedthrough vs. lo frequency (f lo ) and temperature; multiple devices shown ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 undesired sideband (dbc) lo frequency (mhz) t a = ?40c t a = +25c t a = +85c 08570-111 figure 11. sideband suppression vs. lo frequency (f lo ) and temperature; multiple devices shown 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 output ip3 and ip2 (dbm) lo frequency (mhz) t a = ?40c t a = +25c t a = +85c oip2 oip3 08570-112 figure 12. oip3 and oip2 vs. lo frequency (f lo ) and temperature (p out ?2 dbm per tone); multiple devices shown ? 80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 carrier feedthrough (dbm) lo frequency (mhz) t a = ?40c t a = +25c t a = +85c 08570-113 figure 13. carrier feedthrough vs. lo frequency (f lo ) and temperature after nulling at 25c; multiple devices shown ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 undesired sideband nulled (dbc) lo frequency (mhz) t a = ?40c t a = +25c t a = +85c 08570-114 figure 14. sideband suppression vs. lo frequency (f lo ) and temperature after nulling at 25c; multiple devices shown ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ? 20 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 third-order distortion (dbc), second-order distortion (dbc) lo frequency (mhz) third-order distortion second-order distortion t a = ?40c t a = +25c t a = +85c 08570-115 figure 15. second- and third-order distortion vs. lo frequency (f lo ) and temperature
adrf6703 rev. 0 | page 12 of 36 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1k 10k 100k 1m 10m 100m phase noise, lo frequency = 2140mhz (dbc/hz) offset frequency (hz) 2.5khz loop filter 130khz loop filter 08570-116 t a = ?40c t a = +25c t a = +85c figure 16. phase noise vs. offset frequency and temperature, f lo = 2140 mhz ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1k 10k 100k 1m 10m 100m phase noise, lo frequency = 2300mhz (dbc/hz) offset frequency (khz) t a = ?40c t a = +25c t a = +85c 2.5khz loop filter 130khz loop filter 08570-117 figure 17. phase noise vs. offset frequency and temperature, f lo = 2300 mhz ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1k 10k 100k 1m 10m 100m phase noise, lo frequency = 2600mhz (dbc/hz) offset frequency (khz) t a = ?40c t a = +25c t a = +85c 08570-118 2.5khz loop filter 130khz loop filter figure 18. phase noise vs. offset frequency and temperature, f lo = 2600 mhz 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 integr a ted phase noise (rms) lo frequency (mhz) t a = ?40c t a = +25c t a = +85c 08570-119 figure 19. integrated phase noise vs. lo frequency ?150 ?140 ?130 ?120 ?110 ?100 ?90 ? 80 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 phase noise, 100khz offset (dbc/hz) lo frequency (mhz) offset = 1khz offset = 100khz offset = 5mhz 08570-120 t a = ?40c t a = +25c t a = +85c figure 20. phase noise vs. lo frequency at 1 khz, 100 khz, and 5 mhz offsets ?150 ?140 ?130 ?120 ?110 ?100 ?90 ? 80 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 phase noise , 1mhz offset (dbc/hz) lo frequency (mhz) offset = 10khz offset = 1mhz t a = ?40c t a = +25c t a = +85c 08570-121 figure 21. phase noise vs. lo frequency at 10 khz and 1 mhz offsets
adrf6703 rev. 0 | page 13 of 36 ?120 ?110 ?100 ?90 ?80 ? 70 2100 2200 2300 2400 2500 2150 2250 2350 2450 2550 2600 spur level (dbc) lo frequency (mhz) 2 pfd frequency 4 pfd frequency t a = ?40c t a = +25c t a = +85c 08570-122 figure 22. pll reference spurs vs. lo frequency (2 pfd and 4 pfd) at modulator output ?120 ?110 ?100 ?90 ?80 ? 70 ?115 ?105 ?95 ?85 ?75 2100 2200 2300 2400 2500 2150 2250 2350 2450 2550 2600 spur level (dbc) lo frequency (mhz) 1 pfd frequency 3 pfd frequency t a = ?40c t a = +25c t a = +85c 0.5 pfd frequency 08570-123 figure 23. pll reference spurs vs. lo frequency (0.5 pfd, 1 pfd, and 3 pfd) at modulator output 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 v tune (v) lo frequency (mhz) t a = ?40c t a = +25c t a = +85c 08570-124 figure 24. vtune vs. lo frequency and temperature ?120 ?110 ?100 ?90 ?80 ? 70 ?115 ?105 ?95 ?85 ?75 2100 2200 2300 2400 2500 2150 2250 2350 2450 2550 2600 spur level (dbc) lo frequency (mhz) 2 pfd frequency 4 pfd frequency t a = ?40c t a = +25c t a = +85c 08570-125 figure 25. pll reference spurs vs. lo frequency (2 pfd and 4 pfd) at lo output ?120 ?110 ?100 ?90 ?80 ? 70 ?115 ?105 ?95 ?85 ?75 2100 2200 2300 2400 2500 2150 2250 2350 2450 2550 2600 spur level (dbc) lo frequency (mhz) 3 pfd frequency 0.5 , 2 pfd frequency t a = ?40c t a = +25c t a = +85c 08570-126 figure 26. pll reference spurs vs. lo frequency (0.5 pfd, 2 pfd, and 3 pfd) at lo output ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency (hz) 0 8570-127 lo = 2594.13mhz lo = 2306.26mhz lo = 2138.95mhz figure 27. open-loop vco phase noise at 2138.95 mhz, 2306.26 mhz, and 2594.13 mhz
adrf6703 rev. 0 | page 14 of 36 0 10 20 30 40 50 60 70 80 90 100 ?164 ?163 ?162 ?161 ?160 ?159 ?158 ?157 cumulative percentage (%) noise floor (dbm/hz) 2140mhz 2300mhz 2600mhz 08570-128 figure 28. iq modulator noise floor cumulative distributions at 2140 mhz, 2300 mhz, and 2600 mhz ?25 ?20 ?15 ?10 ?5 0 5 10 15 0 50 100 150 200 250 300 frequencuy devi a tion from 2410mhz (mhz) time (s) 08570-129 figure 29. frequency deviatio n from lo frequency at lo = 2.41 ghz to 2.4 ghz vs. lock time ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 ssb output power and lo feedthrough (dbm ) lo frequency (mhz) ssb output power lo feedthrough 08570-130 figure 30. ssb output power and lo f eedthrough with rf output disabled 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 ?40 ?15 10 35 60 85 vpt a t (v) temperature (c) 08570-131 figure 31. vptat voltage vs. temperature
adrf6703 rev. 0 | page 15 of 36 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 return loss (db) lo frequency (mhz) rf out lo input 08570-132 figure 32. input return loss of lo input (lon, lop driven through maba- 007159 1:1 balun) and output retu rn loss of rfout vs. frequency 160 180 200 220 240 260 280 300 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 supply current (ma) lo frequency (mhz) 08570-133 t a = ?40c t a = +25c t a = +85c figure 33. power supply current vs. frequency and temperature (pll and iqmod enabled, lo buffer disabled) 2 1 2600mhz 2100mhz 08570-134 figure 34. smith chart representation of rf output
adrf6703 rev. 0 | page 16 of 36 theory of operation the adrf6703 integrates a high performance iq modulator with a state of the art fractional-n pll. the adrf6703 also integrates a low noise vco. the programmable spi port allows the user to control the fractional-n pll functions and the modulator optimization functions. this includes the capability to operate with an externally applied lo or vco. the quadrature modulator core within the adrf6703 is a part of the next generation of industry-leading modulators from analog devices, inc. the baseband inputs are converted to currents and then mixed to rf using high performance npn transistors. the mixer output currents are transformed to a single-ended rf output using an integrated rf transformer balun. the high performance active mixer core, coupled with the low-loss rf transformer balun results in an exceptional oip3 and op1db, with a very low output noise floor for excel- lent dynamic range. the use of a passive transformer balun rather than an active output stage leads to an improvement in oip3 with no sacrifice in noise floor. at 2140 mhz the adrf6703 typically provides an output p1db of 14.2 dbm, oip3 of 33.2 dbm, and an output noise floor of ?159.6 dbm/hz. typical image rejection under these conditions is ?52.3 dbc with no additional i and q gain compensation. pll + vco the fractional divide function of the pll allows the frequency multiplication value from refin to the lop/lon outputs to be a fractional value rather than restricted to an integer as in traditional plls. in operation, this multiplication value is int + (frac/mod) where int is the integer value, frac is the fractional value, and mod is the modulus value, all of which are programmable via the spi port. in previous fractional-n pll designs, the fractional multiplication was achieved by periodically changing the fractional value in a deterministic way. the downside of this was often spurious components close to the fundamental signal. in the adrf6703 , a sigma delta modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function. basic connections for operation figure 35 shows the basic connections for operating the adrf6703 as they are implemented on the devices evaluation board. the seven power supply pins should be individually decoupled using 100 pf and 0.1 f capacitors located as close as possible to the pins. a single 10 f capacitor is also recom- mended. the three internal decoupling nodes (labeled decl3, decl2, and decl1) should be individually decoupled with capacitors as shown in figure 35 . the four i and q inputs should be driven with a bias level of 500 mv. these inputs are generally dc-coupled to the outputs of a dual dac (see the dac-to-iq modulator interfacing and iq filtering sections for more information). a 1 v p-p (0.353 v rms) differential sine wave on the i and q inputs results in a single sideband output power of 4.95 dbm (at 2140 mhz) at the rfout pin (this pin should be ac-coupled as shown in figure 35 ). this corresponds to an iq modulator voltage gain of 0.95 db. the reference frequency for the pll (typically 1 v p-p between 12 mhz and 160 mhz) should be applied to the refin pin, which should be ac-coupled. if the refin pin is being driven from a 50 source (for example, a lab signal generator), the pin should be terminated with 50 as shown in figure 35 (an rf drive level of +4 dbm should be applied). multiples or fractions of the refin signal can be brought back off-chip at the multiplexer output pin (muxout). a lock-detect signal and an analog voltage proportional to the ambient temperature can also be brought out on this pin by setting the appropriate bits on (db21-db23) in register 4 (see the register description section). external lo the internally generated local oscillator (lo) signal can be brought off-chip as either a 1 lo or a 2 lo (via pins lop and lon) by asserting the losel pin and making the appro- priate internal register settings. the lo output must be disabled whenever the rf output of the iq modulator is disabled. the lop and lon pins can also be used to apply an external lo. this can be used to bypass the internal pll/vco or if operation using an external vco is desired. to turn off the pll register 6, bits[20:17] must be zero.
adrf6703 rev. 0 | page 17 of 36 mux rset nc notes 1. nc = no connect. do not connect to this pin. cp vtune losel lon lop 2:1 mux vco core temp sensor decl2 decl1 decl3 rfout open ? + charge pum p 250a, 500a (default), 750a, 1000a prescaler 2 muxout gnd refin adrf6703 phase frequency detector third-order fractional interpolator fraction reg modulus integer reg n counter 21 to 123 2 2 4 divider 2 spi interface c43 10f (0603) c14 22pf (0603) cp test point (open) c13 6.8pf (0603) c40 22pf (0603) c3 100pf (0402) r3 open (0402) v cc vtune open c15 2.7nf (1206) c2 open (0402) c1 100pf (0402) r38 open (0402) r37 0 ? (0402) r2 open (0402) c42 10f (0603) c17 0.1f (0402) r63 open (0402) r65 10k ? (0402) r9 10k ? (0402) r12 0 ? (0402) r10 3k ? (0603) r62 0 ? (0402) r11 open (0402) rfout c16 100pf (0402) c41 open (0603) c11 0.1f (0402) c12 100pf (0402) r16 open (0402) c29 100pf (0402) c5 100pf (0402) r39 10k ? (0402) vcc s1 r40 10k ? (0402) c6 100pf (0402) r73 49.9 ? (0402) see text 5 ext lo ref_in refout open 1 43 maba-007159 r20 0 ? (0402) r43 10k ? (0402) s2 r47 10k ? (0402) vdd vdd vdd vdd vdd vdd vdd enop clk data le c9 0.1f (0402) c10 100pf (0402) c27 0.1f (0402) c26 100pf (0402) c25 0.1f (0402) c24 100pf (0402) c23 0.1f (0402) c22 100pf (0402) c20 0.1f (0402) c21 100pf (0402) c19 0.1f (0402) c18 100pf (0402) c7 0.1f (0402) vcc red +5v c28 10f (3216) c8 100pf (0402) qn qp 2 0/90 ip in qn qp ip in r23 open (0402) le (usb) data (usb) clk (usb) 08570-023 figure 35. basic connections for operation (loop filter set to 130 khz) loop filter the loop filter is connected between the cp and vtune pins. the return for the loop filter components should be to pin 40 (decl3). the loop filter design in figure 35 results in a 3 db loop bandwidth of 130 khz. the adrf6703 closed loop phase noise was also characterized using a 2.5 khz loop filter design. the recommended components for both filter designs are shown in table 8 . for assistance in designing loop filters with other characteristics, download the most recent revision of adisimpll? from www.analog.com/adisimpll . operation with an external vco is possible. in this case, the return for the loop filter components is ground (assuming a ground reference on the external vco tuning input). the output of the loop filter is connected to the external vcos tuning pin. the output of the vco is brought back into the device on the lop and lon pins (using a balun if necessary). table 8. recommended loop filter components component 130 khz loop filter 2.5 khz loop filter c14 22 pf 0.1 f r10 3 k 68 c15 2.7 nf 4.7 f r9 10 k 270 c13 6.8 pf 47 nf r65 10 k 0 c40 22 pf open r37 0 0 r11 open open r12 0 0
adrf6703 rev. 0 | page 18 of 36 dac-to-iq modulator interfacing the adrf6703 is designed to interface with minimal components to members of the analog devices, inc., family of txdacs?. these dual-channel differential current output dacs provide an output current swing from 0 ma to 20 ma. the interface described in this section can be used with any dac that has a similar output. an example of an interface using the ad9122 txdac is shown in figure 36. the baseband inputs of the adrf6703 require a dc bias of 500 mv. the average output current on each of the outputs of the ad9122 is 10 ma. therefore, a single 50 resis- tor to ground from each of the dac outputs results in an average current of 10 ma flowing through each of the resistors, thus producing the desired 500 mv dc bias for the inputs to the adrf6703 . rbip 50? rbin 50? out1_n out1_p ip in ad9122 adrf6703 rbqn 50? rbqp 50? out2_p out2_n qp qn 08570-033 figure 36. interface between the ad9122 and adrf6703 with 50 resistors to ground to establish the 500 mv dc bias for the adrf6703 baseband inputs the ad9122 output currents have a swing that ranges from 0 ma to 20 ma. with the 50 resistors in place, the ac voltage swing going into the adrf6703 baseband inputs ranges from 0 v to 1 v (with the dac running at 0 dbfs). so the resulting drive signal from each differential pair is 2 v p-p differential with a 500 mv dc bias. adding a swing-limiting resistor the voltage swing for a given dac output current can be reduced by adding a third resistor to the interface. this resistor is placed in the shunt across each differential pair, as shown in figure 37. it has the effect of reducing the ac swing without changing the dc bias already established by the 50 resistors. rbip 50 ? rbin 50 ? in ip ad9122 adrf6703 rbqn 50 ? rbqp 50 ? r sl2 (see text) r sl1 (see text) out1_n out1_p out2_p out2_n qp qn 08570-034 figure 37. ac voltage swing reduction through the introduction of a shunt resistor between the differential pair the value of this ac voltage swing limiting resistor(r sl as shown in figure 37) is chosen based on the desired ac voltage swing and iq modulator output power. figure 38 shows the relation- ship between the swing-limiting resistor and the peak-to-peak ac swing that it produces when 50 bias-setting resistors are used. a higher value of swing-limiting resistor will increase the output power of the adrf6703 and signal-to-noise ratio (snr) at the cost if higher intermodulation distortion. for most applications, the optimum value for this resistor will be between 100 and 300 . when setting the size of the swing-limiting resistor, the input impedance of the i and q inputs should be taken into account. the i and q inputs have a differential input resistance of 920 . as a result, the effective value of the swing-limiting resistance is 920 in parallel with the chosen swing-limiting resistor. for example, if a swing-limiting resistance of 200 is desired (based on figure 37), the value of r sl should be set such that 200 = (920 r sl )/(920 + r sl ) resulting in a value for r sl of 255 . 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 100 1000 10000 differenti a l swing (v p-p) r sl ( ? ) 08570-235 figure 38. relationship between the ac swing-limiting resistor and the peak-to-peak voltage swing with 50 bias-setting resistors
adrf6703 rev. 0 | page 19 of 36 0 0.2 0.4 0.6 0.8 1.0 1.2 400 500 600 700 800 900 1000 0 100 200 300 400 500 capacitance (pf) resistance ( ? ) baseband frequency (mhz) resistance capacitance 08570-141 iq filtering an antialiasing filter must be placed between the dac and modulator to filter out nyquist images and broadband dac noise. the interface for setting up the biasing and ac swing discussed in the adding a swing-limiting resistor section, lends itself well to the introduction of such a filter. the filter can be inserted between the dc bias setting resistors and the ac swing-limiting resistor. doing so establishes the input and output impedances for the filter. unless a swing-limiting resistor of 100 is chosen, the filter must be designed to support different source and load impedances. in addition, the differential input capacitance of the i and q inputs (1 pf) should be factored into the filter design. modern filter design tools allow for the simulation and design of filters with differing source and load impedances as well as inclusion of reactive load components. figure 40. differential baseband input r and input c equivalents (shunt r, shunt c) device programming and register sequencing baseband bandwidth figure 39 shows the frequency response of the adrf6703 s baseband inputs. this plot shows 0.5 db and 3 db bandwidths of 350 mhz and 750 mhz respectively. any flatness variations across frequency at the adrf6703 rf output have been calibrated out of this measurement. the device is programmed via a 3-pin spi port. the timing requirements for the spi port are shown in table 3 and figure 2 . eight programmable registers, each with 24 bits, control the operation of the device. the register functions are listed in table 9 . the eight registers should initially be programmed in reverse order, starting with register 7 and finishing with register 0. once all eight registers have been initially programmed, any of the registers can be updated without any attention to sequencing. ?10 ?8 ?6 ?4 ?2 0 2 4 10 100 1000 baseband frequency response (dbc) bb frequency (mhz) 08570-234 software is available on the adrf6703 product page at www.analog.com that allows programming of the evaluation board from a pc running windows? xp or windows vista. to operate correctly under windows xp, version 3.5 of microsoft .net must be installed. to run the software on a windows 7 pc, xp emulation mode must be used (using virtual pc). figure 39. baseband bandwidth
adrf6703 rev. 0 | page 20 of 36 register summary table 9. register functions register function register 0 integer divide control (for the pll) register 1 modulus divide control (for the pll) register 2 fractional divide control (for the pll) register 3 - modulator dither control register 4 pll charge pump, pfd, and reference path control register 5 lo path and modulator control register 6 vco control and vco enable register 7 external vco enable
adrf6703 rev. 0 | page 21 of 36 register description register 0integer divide control (default: 0x0001c0) with register 0, bits[2:0] set to 000, the on-chip integer divide control register is programmed as shown in figure 41 . divide mode divide mode determines whether fractional mode or integer mode is used. in integer mode, the rf vco output frequency (f vco ) is calculated by f vco = 2 f pfd ( int ) (1) where: f vco is the output frequency of the internal vco. f pfd is the frequency of operation of the phase-frequency detector. int is the integer divide ratio value (21 to 123 in integer mode). integer divide ratio the integer divide ratio bits are used to set the integer value in equation 2. the int, frac, and mod values make it possible to generate output frequencies that are spaced by fractions of the pfd frequency. the vco frequency (f vco ) equation is f vco = 2 f pfd ( int + ( frac / mod )) (2) where: int is the preset integer divide ratio value (24 to 119 in fractional mode). mod is the preset fractional modulus (1 to 2047). frac is the preset fractional divider ratio value (0 to mod ? 1). divide mode db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0000000000000dmid6id5id4id3id2id1id0c3(0)c2(0)c1(0) dm 0 1 id6 id5 id4 id3 id2 id1 id0 0010101 0010110 0010111 0011000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0111000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1110111 1111000 1111001 1111010 1111011 ... ... 119 120 (integer mode only) integer divide ratio 21 (integer mode only) 22 (integer mode only) 23 (integer mode only) 24 ... ... 56 (default) integer integer divide ratio control bits divide mode fractional (default) 121 (integer mode only) 122 (integer mode only) 123 (integer mode only) reserved 08570-014 figure 41. register 0integer divide control register map
adrf6703 rev. 0 | page 22 of 36 register 1modulus divide control (default: 0x003001) with register 1, bits[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in figure 42 . modulus value the modulus value is the preset fractional modulus ranging from 1 to 2047. register 2fractional divide control (default: 0x001802) with register 2, bits[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in figure 43 . fractional value the frac value is the preset fractional modulus ranging from 0 to adrf6703 rev. 0 | page 23 of 36 register 3- modulator dither control (default: 0x10000b) with register 3, bits[2:0] set to 011, the on-chip - modulator dither control register is programmed as shown in figure 44 . the recommended and default setting for dither enable is enabled (1). the default value of the dither magnitude (15) should be set to a recommended value of 1. the dither restart value can be programmed from 0 to 2 17 ? 1, though a value of 1 is typically recommended. dither enable db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 dith1 dith0 den dv16 dv15 dv14 dv13 dv12 dv11 dv10 dv9 dv8 dv7 dv6 dv5 dv4 dv3 dv2 dv1 dv0 c3(0) c2(1) c1(1) dith1 dith0 00 01 10 11 den 0 1 dither magnitude dither restart value control bits dither magnitude 15 (default) 7 3 1 (recommended) dither enable disable enable (default, recommended) dv16 dv15 dv14 dv13 dv12 dv11 dv10 dv9 dv8 dv7 dv6 dv5 dv4 dv3 dv2 dv1 dv0 0000 0 0 00000000001 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1111 1 1 1111111111 dv2 0 ... ... 11 0x00001 (default) ... ... 0x1ffff dither restart value 08570-017 figure 44. register 3- modula tor dither control register map
adrf6703 rev. 0 | page 24 of 36 register 4pll charge pump, pfd, and reference path control (default: 0x0aa7e4) with register 4, bits[2:0] set to 100, the on-chip charge pump, pfd, and reference path control register is programmed as shown in figure 45 . cp current the nominal charge pump current can be set to 250 a, 500 a, 750 a, or 1000 a using db10 and db11 of register 4 and by setting db18 to 0 (cp reference source). in this mode, no external rset is required. if db18 is set to 1, the four nominal charge pump currents (i nominal ) can be externally tweaked according to the following equation: ? ? ? ? ? ? ? ? ? = 8.37 4.217 nominal cp set i i r (3) where i cp is the base charge pump current in microamps. the pfd phase offset multiplier ( pfd,ofs ), which is set by bits[16:12] of register 4, causes the pll to lock with a nominally fixed phase offset between the pfd reference signal and the divided-down vco signal. this phase offset is used to linearize the pfd-to-cp transfer function and can improve fractional spurs. the magnitude of the phase offset is deter- mined by the following equation: multcp ofspfd i , , 5.22(deg) =? (4) the default value of the phase offset multiplier (10 22.5) should be set to a recommended value of 6 22.5. this phase offset can be either positive or negative depending on the value of db17 in register 4. the reference frequency applied to the pfd can be manipulated using the internal reference path source. the external reference frequency applied can be internally scaled in frequency by 2, 1, 0.5, or 0.25. this allows a broader range of reference frequency selections while keeping the reference frequency applied to the pfd within an acceptable range. the device also has a muxout pin that can be programmed to output a selection of several internal signals. the default mode is to provide a lock-detect output to allow the user to verify when the pll has locked to the target frequency. in addition, several other internal signals can be passed to the muxout pin as described in figure 35 .
adrf6703 rev. 0 | page 25 of 36 cp current ref source pfd pol cp source db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 rms2 rms1 rms0 rs1 rs0 cpm cpbd cpb4 cpb3 cpb2 cpb1 cpb0 cpp1 cpp0 cps cpc1 cpc0 pe1 pe0 pab1 pab0 c3(1) c2(0) c1(0) cpc1 cpc0 00 01 10 11 cps 0 1 cpp1 cpp0 00 01 10 11 cpb4 cpb3 cpb2 cpb1 cpb0 0000 0 0000 1 0011 0 0101 0 1000 0 1111 1 cpbd 0 1 cpm 0 1 rs1 rs0 00 10 01 11 rms2 rms1 rms0 000 001 010 011 100 101 110 111 10 22.5/i cp,mult (default) 16 22.5/i cp,mult 31 22.5/i cp,mult pfd phase offset multiplier 0 22.5/i cp,mult 1 22.5/i cp,mult 6 22.5/i cp,mult (recommended) both on pump down pump up tristate (default) ref ouput mux select input ref path pfd phase offset multiplier cp current cp control pfd edge control bits pfd anti- backlash delay pe0 0 1 reference path edge sensitivity falling edge rising edge (default) pab1 pab0 00 10 01 11 pfd antibacklash delay 0ns (default) 0.5ns 0.75ns 0.9ns charge pump control 0.5 refin (buffered) charge pump control source control based on state of db7/db8 (cp control) control from pfd (default) ref output mux select lock detect (default) vptat refin (buffered) pfd phase offset polarity negative positive (default) charge pump current reference source internal (default) external 0.25 refin charge pump current 250a 500a (default) 750a 1000a input ref path source 2 refin refin (default) 0.5 refin 2 refin (buffered) tristate reserved reserved pe1 0 1 divider path edge sensitivity falling edge rising edge (default) 08570-018 figure 45. register 4pll charge pump, pfd, and reference path control register map
adrf6703 rev. 0 | page 26 of 36 register 5lo path and modulator control (default: 0x0000d5) with register 5, bits[2:0] set to 101, the lo path and modulator control register is programmed as shown in figure 46 . the modulator output or the complete modulator can be disabled using the modulator bias enable and modulator output enable addresses of register 5. the lo port (lop and lon pins) can be used to apply an external 2 lo (that is, bypass internal pll) to the iq modulator. a differential lo drive of 0 dbm is recommended. the lo port can also be used as an output where a 2 lo or 1 lo can be brought out and used to drive another mixer. the nominal output power provided at the lo port is 3 dbm. the mode of operation of the lo port is determined by the status of the losel pin (3.3 v lo gic) along with the settings in a number of internal registers (see table 10 ). table 10. lo port configuration 1, 2 lon/lop function losel register 5, bit db5 (ldiv) register 5, bit db4 (lxl) register 5, bit db3 (ldrv) input (2 lo) 0 x 1 0 output (disabled) 0 x 0 0 output (1 lo) 0 0 0 1 output (1 lo) 1 0 0 0 output (1 lo) 1 0 0 1 output (2 lo) 0 1 0 1 output (2 lo) 1 1 0 0 output (2 lo) 1 1 0 1 1 x = dont care. 2 losel should not be left floating. the internal vco of the device can also be bypassed. in this case, the charge pump output dr ives an external vco through the loop filter. the loop is completed by routing the vco into the device through the lo port. reserved mod bias enable rf output enable lo output divider lo in/out control lo output driver enable db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 mbe db6 db5 db4 db3 db2 db1 db0 0 0 0 0 rfen ldiv lxl ldrv c3(1) c2(0) c1(1) ldrv 0 1 ldiv 0 1 divide by 1 divide by 2 (default) lo output driver enable driver off (default) driver on rfen 0 1 disable enable (default) rf output enable lo output divide mode control bits lxl 0 1 lo output (default) lo input lo input/output control mbe 0 1 disable enable (default) mod bias enable 000 0 0 000 000 0 08570-019 figure 46. register 5lo path and modulator control register map
adrf6703 rev. 0 | page 27 of 36 register 6vco control and vco enable (default: 0x1e2106) with register 6, bits[2:0] set to 110, the vco control and enable register is programmed as shown in figure 47 . the vco tuning band is normally selected automatically by the band calibration algorithm, althou gh the user can directly select the vco band using register 6. the vco bs src bit (db9) determines whether the result of the calibration algorithm is used to select the vco band or if the band selected is based on the value in vco band select (db8 to db3). the vco amplitude can be controlled through register 6. the vco amplitude setting can be controlled between 0 and 63. the default value of 8 should be set to a recommended value of 63. the internal vcos can be disabled using register 6. the internal charge pump can be disabled through register 6. by default, the charge pump is enabled. to turn off the pll (for example, if the adrf6703 is being driven by an external lo), set register 6, bits[20:17] to zero. register 7external vco enable with register 7, bits[2:0] set to 111, the external vco control register is programmed as shown in figure 48 . the external vco enable bit allows the use of an external vco in the pll instead of the internal vco. this can be advantageous in cases where the internal vco is not capable of providing the desired frequency or where the internal vcos phase noise is higher than desired. by setting this bit (db22) to 1, and setting register 6, bits[15:10] to 0, the internal vco is disabled, and the output of an external vco can be fed into the part differ- entially on pin 38 and pin 37 (lop and lon). because the loop filter is already external, the output of the loop filter simply needs to be connected to the external vcos tuning voltage pin. charge pump enable 3.3v ldo enable vco enable vco switch vco bw sw ctrl vbsrc 0 1 vco en vco ldo enable vco amplitude reserved vco band select from spi vbs[5:0] vco band select from spi 0x00 default 0x20 charge pump enable 0x01 ?. 0x00 0 ?. ?. 0x18 8 (default) ?. ?. 0x2b 43 ?. ?. 0x3f 63 (recommended) 0x3f vco bw cal and sw source control band cal (default) vco sw 0 1 vco switch control from spi regular (default) band cal spi vco enable disable enable (default) db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 control bits db23 cpen l3en vco en vco sw vc5 vc4 vc3 vc2 vc1 vc0 vbsrc vbs5 vbs4 vbs3 vbs2 vbs1 vbs0 c3(1) c2(1) c1(0) lven vc[5:0] vco amplitude 0 1 lven vco ldo enable disable enable (default) 0 1 l3en 3.3v ldo enable disable enable (default) 0 1 cpen disable enable (default) 0 1 000 08570-020 figure 47. register 6vco contro l and vco enable register map db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 xvco external vco enable res 0 0 00000000000000000c3(1)c2(1)c1(1) reserved control bits xvco 0 1 internal vco (default) external vco external vco enable 08570-021 figure 48. register 7external vco enable register map
adrf6703 rev. 0 | page 28 of 36 characterization setups figure 49 and figure 50 show characterization bench setups used to characterize the adrf6703 . the setup shown in figure 49 was used to do most of the testing. an automated vee program was used to control equipment over the ieee bus. the setup was used to measure ssb, oip2, oip3, op1db, lo, and usb null. for phase noise and reference spurs measurements, see the phase noise setup on figure 50 . phase noise was measured on lo and modulator output. pc control connected to system via usb to gpib adapter aeroflex ifr 3416 frequency generator (with baseband outputs at 1mhz) 34980a with 34950 and (2) 34921 modules rohde and schwartz smt 06 signal generator (refin) agilent e4440a psa spectrum analyzer adrf670x test rack assembly (internal v co configuration) all instruments are connected in daisy chain fashion via gbip cable unless otherwise noted. +5v for vpos to 34950 module baseband inputs at 1mhz 9-pin dsub connector (register programming) 10-pin connector dc header rf out ref in e3631a power supply (+6v adjusted to 5v) keithley s46 switch system #1 (for rfout and refin on 6 sites) programming and dc cable (6 for multisite) output (ref) input (rfout) keithley s46 switch system #2 (for baseband inputs on 6 sites) 34401a dmm (for supply current measurement) baseband outputs (in, ip, qn, qp) 6db 6db adrf6703 eval board 08570-043 figure 49. general characterization setup
adrf6703 rev. 0 | page 29 of 36 adrf670x phase noise stand setup all instruments are connected in daisy chain fashion via gbip cable unless otherwise noted. rohde and schwartz sma 100 signal generator agilent e3631a power supply agilent 34401a dmm (in dc i mode, supply current measurement) agilent e5052 signal source analyzer 34980a multifunction switch (with 34950 and 34921 modules) agilent e4440a spectrum analyzer keithley s46 switch system 1 (for baseband inputs on 6 sites) ifr 3416 signal generator (baseband source) keithley s46 switch system 2 (for if out and refin on 6 sites) input dc 10 pin connector (dc measurement, +5v pos) and 9 pin dsub connector (vco and pll programming) refin if out refin lo out baseband inputs (ip, in, qp, qn) pc control connected to system via usb to gpib adapter adrf6703 eval board 08570-044 figure 50. characterization setup for phase noise and reference spur measurements
adrf6703 rev. 0 | page 30 of 36 evaluation board to operate correctly under windows xp, version 3.5 of microsoft .net must be installed. to run the software on a windows 7 pc, xp emulation mode must be used (using virtual pc). figure 52 shows the schematic of the devices rohs-compliant evaluation board. this board was designed using rogers 4350 material to minimize losses at high frequencies. fr4 material would also be adequate but with the slightly higher trace loss of this material. 08570-135 whereas the on-board usb interface circuitry of the evaluation board is powered directly from the pc, the main section of the evaluation board requires a separate 5 v power supply. the evaluation board is designed to operate using the internal vco (default configuration) of the device or with an external vco. to use an external vco, r62 and r12 should be removed. 0 resistors should be placed in r63 and r11. a side-launched sma connector (johnson 142-0701-851) must be soldered to the pad labeled vtune. the input of the external vco should be connected to the vtune sma connector and a portion of the vcos output should be connected to the ext lo sma connector. in addition to these hardware changes, internal register settings must also be changed (as detailed in the register description section) to enable operation with an external vco. additional configuration options for the evaluation board are described in table 11 . figure 51. control software opening menu the serial port of the adrf6703 can be programmed from a pcs usb port (a usb cable is provided with the evaluation board). the on-board usb interface circuitry can if desired be bypassed by removing the 0 resistors, r15, r17, and r18 (see figure 52 ) and driving the adrf6703 serial interface through the p3 4-pin header (p3 must be first installed, samtec tsw- 104-08-g-s). figure 51 shows the opening window of the software where the user selects the device being programmed. figure 55 shows a screen shot of the control softwares main controls with the default settings displayed. the text box in the bottom left corner provides an immediate indication of whether the software is successfully communicating with the evaluation board. if the evaluation board is connected to the pc via the usb cable provided and the software is successfully communicating with the on-board usb circuitry, this text box shows the following message: adrf6x0x eval board connected . evaluation board control software usb-based programming software is available to download from the adrf6703 product page at www.analog.com (evaluation board software rev 6.1.0). to install the software, download and extract the zip file. then run the following installation file: adrf6x0x_6p1p0_customer_installer.exe .
adrf6703 rev. 0 | page 31 of 36 mux rset nc notes 1. nc = no connect. do not connect to this pin. cp vtune losel lon lop 2:1 mux vco core temp sensor decl2 decl1 decl3 rfout open ? + charge pum p 250a, 500a (default), 750a, 1000a prescaler 2 muxout gnd refin adrf6703 phase frequenc y detector third-order fractional interpolator fraction reg modulus integer reg n counter 21 to 123 2 2 4 divider 2 spi interface c43 10f (0603) c14 22pf (0603) cp test point (open) c13 6.8pf (0603) c40 22pf (0603) c3 100pf (0402) r3 open (0402) vcc vtune open c15 2.7nf (1206) c2 open (0402) c1 100pf (0402) r38 open (0402) r37 0 ? (0402) r2 open (0402) c42 10f (0603) c17 0.1f (0402) r63 open (0402) r65 10k ? (0402) r9 10k ? (0402) r12 0 ? (0402) r10 3k? (0603) r62 0 ? (0402) r11 open (0402) rfout c16 100pf (0402) c41 open (0603) c11 0.1f (0402) c12 100pf (0402) r16 open (0402) c29 100pf (0402) c5 100pf (0402) r39 10k ? (0402) vcc s1 r40 10k ? (0402) c6 100pf (0402) r73 49.9 ? (0402) see text 5 ext lo ref_in refout open 1 43 maba-007159 r20 0 ? (0402) r43 10k ? (0402) s2 r47 10k ? (0402) vdd vdd vdd vdd vdd vdd vdd enop clk data le c9 0.1f (0402) c10 100pf (0402) c27 0.1f (0402) c26 100pf (0402) c25 0.1f (0402) c24 100pf (0402) c23 0.1f (0402) c22 100pf (0402) c20 0.1f (0402) c21 100pf (0402) c19 0.1f (0402) c18 100pf (0402) c7 0.1f (0402) vcc red +5v c28 10f (3216) c8 100pf (0402) qn qp 2 0/90 ip in qn qp ip in r23 open (0402) le (usb) data (usb) clk (usb) 08570-027 figure 52. evaluation board schematic (loop filter set to 130 khz) 08570-047 figure 53. evaluation board top layer 08570-048 figure 54. evaluation board bottom layer
adrf6703 rev. 0 | page 32 of 36 table 11. evaluation board configuration options component description default condition/option settings s1, r39, r40 lo select. switch and resistors to ground losel pin. the losel pin setting in combination with internal register settings, determines whether the lop/lon pins function as inputs or outputs. with the losel pin grounded, register settings can set the lop/lon pins to be inputs or outputs. ext lo, t3 lo input/output. an ex ternal 1 lo or 2 lo can be applied to this single-ended input connector. alternatively, the internal 1 or 2 lo can be brought out on this pin. the differential lo signal on lop and lon is converted to a single-ended signal using a broadband 1:1 balun (macom maba-007159, 4.5 mhz to 3000 mhz frequency range). the balun footprint on the evaluation board is also designed to accommodate johanson baluns: 3600bl14m050 (1:1, 3.3 ghz to 3.9 ghz) and 3700bl15b050e (1:1, 3.4 ghz to 4 ghz). t3 = macom maba-007159 ext lo sma connector = installed refin sma connector, r73 reference input. the input reference frequency for the pll is applied to this connector. input resistance is set by r73 (49.9 ). f refin = 153.6 mhz r73 = 49.9 refout sma connector, r16 multiplexer output. the refout connector connects directly to the devices muxout pin. the on-board multiplexer can be programmed to bring out the following signals: refin, 2 refin, refin/2, refin/4, temperature sensor output voltage (vptat), lock detect indicator. refout sma connector = open r16 = open cp test point, r38 charge pump test point. the unfiltered charge pump signal can be probed at this test point. note that this pin should not be probed during critical measur ements such as phase noise. cp = open r38 = open c13, c14, c15, c40r9, r10, r37, r65 loop filter. loop filter components. see table 8 r11, r12, r62, r63, vtune sma connector internal vs. external vco. when the internal vco is enabled, the loop filter components connect directly to the vtune pin (pin 39) by installing a 0 resistor in r62. in addition, the loop filter components should be returned to pin 40 (decl3) by installing a 0 resistor in r12. to use an external vco, r62 should be left open. a 0 resistor should be installed in r63, and the voltage input of the vco should be connected to the vtune sma connector. the output of the vco is brought back into the pll via the lo in/out sma connector. in addition, the loop filter components should be returned to ground by installing a 0 resistor in r11. loop filter return. r12 = 0 (0402) r11 = open (0402) r62 = 0 (0402) r63 = open (0402) vtune = open r2 rset. this pin is unused and should be left open. r2 = open (0402) r23, r3 baseband input termination. termination resistors for the baseband filter of the dac can be placed on r23 and r3. in addition to terminating the baseband filters, these resistors also scale down the baseband voltage from the dac without changing the bias level. these resistors are generally set in the 100 to 300 range. r3 = r23 = open (0402) p3 4-pin header, r15, r17, r18 usb circuitry bypass. the usb circuitry can be bypassed, allowing for the serial port of the adrf6703 to be driven directly. p3 (samtec tsw-104-08-g-s) must be installed, and 0 resistors (r15, r17 and r18) must be removed. p3 = open r15, r17, r18 = 0 (0402)
adrf6703 rev. 0 | page 33 of 36 08570-136 figure 55. main controls of the evaluation board control software
adrf6703 rev. 0 | page 34 of 36 08570-028 figure 56. usb interface circuitry on the customer evaluation board
adrf6703 rev. 0 | page 35 of 36 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) compliant to jedec standards mo-220-vjjd-2 072108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 57. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-1) dimensions shown in millimeters ordering guide model 1 temperature range (c) package description package option adrf6703acpz-r7 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adrf6703-evalz evaluation board 1 z = rohs compliant part.
adrf6703 rev. 0 | page 36 of 36 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08570-0-6/11(0)

▲Up To Search▲

Price & Availability of ADRF6702

	To Download ADRF6702 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .